Integrated multimedia system
US7961756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Nov 15, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications processor includes a first upper layer module to execute one or more upper layer protocols and a data link layer module to execute a data link layer protocol. A host processor includes a second upper layer module to execute the one or more upper layer protocols. A switching module causes the communications processor to operate in a first state or a second state. The communications processor executes only the data link layer protocol and none of the one or more upper layer protocols when the communications processor operates in the first state, and executes the data link layer protocol and the one or more upper layer protocols when the communications processor operates in the second state. The power saving module prevents the host processor from executing the one or more upper layer protocols executed by the communications processor when the communications processor operates in the second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.