Flexible hardware architecture for ECC/HECC based cryptography
US7961872B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Mar 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/122
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.