Multiple independent levels of security (MILS) certifiable RAM paging system
US7962702B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Feb 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to an integrated circuit, a method and a system for executing a sequence of instruction loaded from an external storage element and ensuring the authenticity of the sequence of instructions via RAM paging. In one embodiment, the integrated circuit includes a processor for executing a sequence of instructions loaded from an external storage element. To ensure the authenticity of the sequence of instructions from the external storage element, the processor supports Multiple Independent Levels of Security (MILS) or another partitioning scheme. A zeroizer is included to zeroize the on-die memory banks thereby ensuring that the processor is incapable of accessing residual sequences of instructions as loaded and stored from the external storage element thereby ensuring the authenticity of the sequence of instructions executed by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.