Branch loop performance enhancement
US7962724B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Nov 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for management of resource allocation for speculative fetched instructions following small backward branch instructions. An instruction fetch unit speculatively prefetches a memory line for each fetched memory line. Each memory line may have a small backward branch instruction, which is a backward branch instruction that has a target instruction within the same memory line. For each fetched memory line, the instruction fetch unit determines if a small backward branch instruction exists among the instructions within the memory line. If a small backward branch instruction is found and predicted taken, then the instruction fetch unit inhibits the speculative prefetch for that particular thread. The speculative prefetch may resume for that thread after the branch loop is completed. System resources may be better allocated during the iterations of the small backward branch loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.