Unified memory architecture for recording applications
US7962833B2 · kind B2 · utility
1Cited by
25References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2009 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Oct 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/10787
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit, a second circuit and a disc. The first circuit may be configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on the data blocks with a delta syndrome based iterative Reed-Solomon decoding. The second circuit may be configured (i) to decode corrected video data into a video format in a first state, (ii) encode the corrected video data in a second state and (iii) share an external memory between the first circuit and the second circuit. The disc may be configured to store encoded video data in the second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.