Semiconductor integrated circuit device and a manufacturing method for the same
US7964457B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2009 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Aug 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
Abstract
Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.