Hardened current mode logic (CML) voter circuit, system and method
US7965098B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2008 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Dec 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.