Combined processing and non-volatile memory unit array
US7965101B2 · kind B2 · utility
1Cited by
4References
7Claims
0Family size
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Key dates
| Filing date | Feb 26, 2010 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Feb 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.