Compensation techniques for reducing power consumption in digital circuitry
US7965133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Apr 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00369
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.