SAR ADC
US7965218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Aug 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.