Data processing device adaptable to variable external memory size and endianess
US7966432B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2005 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jan 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external me…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.