Integrated circuit design structure for an asychronous data interface
US7966435B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2008 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.