Apparatus, system, and method for a fast data return memory controller
US7966439B1 · kind B1 · utility
18Cited by
32References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 24, 2004 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jan 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.