Patent · US Active

Cache architecture for a processing unit providing reduced power consumption in cache operation

US7966452B2 · kind B2 · utility

0Cited by

2References

14Claims

0Family size

Assignee

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations · US

Inventor

Qing Yang · Pleasanton, US

Key dates

Filing date	Jan 22, 2008
Grant date	Jun 21, 2011
Priority date	—
Expiry date	Oct 9, 2029

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.