Method and apparatus for power reduction in iterative decoders
US7966505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2005 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Jul 22, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0057
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There are provided a method, an apparatus and a computer program product for reducing power consumption in an iterative decoder. The apparatus includes a memory device and an iteration termination device. The memory device is for storing a bit number difference indicating a number of bits that are different between a decoded codeword for a current iteration and a decoded codeword for a previous iteration, for each iteration of the iterative decoder prior to a maximum number of iterations. The iteration termination device is for comparing the bit number difference to a pre-specified bit number difference threshold value, incrementing a confidence value when the bit number difference exceeds the pre-specified bit number difference threshold value, and terminating further iterations of the iterative decoder when the confidence value exceeds a pre-specified confidence threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.