Patent · US Active

Method and apparatus for automatic scan completion in the event of a system checkstop

US7966536B2 · kind B2 · utility

8Cited by
10References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 11, 2008
Grant dateJun 21, 2011
Priority date
Expiry dateJul 30, 2029

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/2236
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method for automatic scan completion in the event of a system checkstop in a processor. The processor includes: a processor register; a millicode interface connected between the processor register and a checkstop scan controller; a checkstop logic circuit connected between the checkstop scan controller and a checkstop scan engine; and a scan chain engine and a scan chain connected to the checkstop scan engine. The method includes (a) upon occurrence of a checkstop serially reading data from a processor register and serially writing the data to latches of a scan chain register; and (b) upon occurrence of a system checkstop during (a), stopping the reading and writing and moving data sent before the system checkstop from latches of the scan chain where the data was stored when the system checkstop occurred to latches where the data would have been stored if the system checkstop had not occurred.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.