Cyclic comparison method for low-density parity-check decoder
US7966543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cyclic comparison method for an LDPC decoder. The nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed by the corresponding comparator to obtain k first level sequences. Next, pairs of two elements selected from the k elements are used to form k second level sequences. The preceding step is repeated k×┌log2(k−1)┐ times to obtain k output results. Either of one first level sequences and one output results contains (k−1) elements. The first level sequences are compared with the output results to determine whether they are identical. If they are identical, the process stops. If they are not identical, the abovementioned step is repeated to obtain new output results. The cyclic comparison method of the present invention needs only k×┌log2(k−1)┐ comparisons to obtain output results. Thus, the present invention can reduce the number of basic operations and can apply to any input number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.