Loading the input memory of an LDPC decoder with data for decoding
US7966544B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2007 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Apr 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N−K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.