Place-and-route layout method with same footprint cells
US7966596B2 · kind B2 · utility
8Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Jun 21, 2011 |
| Priority date | — |
| Expiry date | Aug 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.