Electrical test structure to detect stress induced defects using diodes
US7968878B2 · kind B2 · utility
5Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Jan 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.