Semiconductor device

US7968956B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kosuke Tatsumura · Yokohama, JP
• Masakazu GOTO · Tsukuba, JP
• Reika Ichihara · Yokohama, JP
• Masato Koyama · Miura, JP
• Shigeru Kawanaka · Yokohama, JP
• Kazuaki Nakajima · Tokyo, JP

Key dates

• Filing date: Feb 19, 2009
• Grant date: Jun 28, 2011
• Expiry date: Jun 8, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.