Circuit to reduce duty cycle distortion
US7969224B2 · kind B2 · utility
1Cited by
18References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2009 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Jul 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.