Digital correction of nonlinearity errors of multibit delta-sigma digital to analog converters
US7969335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.