Sigma-delta modulator including truncation and applications thereof
US7969341B2 · kind B2 · utility
35Cited by
32References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2010 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Aug 31, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/304
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.