Method and apparatus for improving SRAM write operations
US7969759B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Apr 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first access transistor, first and second pull-up transistors, a depletion transistor, and first and second pull-down transistors. The first access transistor is connected to a word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and to the first data node and the second pull-down transistor is connected to the depletion transistor and to the second data node. The depletion transistor is connected to the word line and to the second power supply point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.