Thyristor-based memory array having lines with standby voltages
US7969777B1 · kind B1 · utility
20Cited by
24References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Dec 1, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.