Barrier synchronization method, device, and multi-core processor
US7971029B2 · kind B2 · utility
15Cited by
6References
13Claims
0Family size
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Key dates
| Filing date | Dec 15, 2009 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Dec 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/522
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.