Integrated waking/while-awake power management system with breaking distance timer for high wake-up latency portion of hardware
US7971086B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2007 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Apr 29, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for activating and deactivating a hardware device including a first stage electronic deactivation unit operative, responsive to a deactivation request, to perform a first deactivation operation including deactivation of a first portion of the hardware device having low wake-up latency at a first time, a second stage electronic deactivation unit including a breaking distance timer activated subsequently to the deactivation request and operative to deactivate a second portion of the hardware device having high wake-up latency at a subsequent second time separated from the first time, and a power management system including a power source and a power supply regulator operative to control the supply of power in accordance with a selectable one of a plurality of regulator settings, selected using a hardware setting selector. Responsive to a wakeup event, the first portion of the hardware device is reactivated and the breaking distance timer is deactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.