Automated scan testing of DDR SDRAM
US7971111B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2010 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for scan testing a memory. The controller includes a control state machine for controlling the scan process, a test sequence stored in a random access memory used by the control state machine for controlling an actual memory test, a pattern generation data unit responsive to the control state machine for generating a test pattern that is written to and read from a memory under test, a configuration register read by the control state machine for configuring the controller and a fault location register written to by the control state machine for storing locations of defects in the memory. The controller is used to auto scan a memory in real time, interleaved with other processes accessing the memory. The controller has several modes of operation including operating in a periodic burst mode to conserve power and in a background mode so as not to interfere with other processes accessing the scanned memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.