Systems and methods for prioritizing error correction data
US7971125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2007 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | Apr 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.