Method, system, and program product for automated verification of gating logic using formal verification
US7971166B2 · kind B2 · utility
2Cited by
21References
23Claims
0Family size
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Key dates
| Filing date | Jun 15, 2008 |
| Grant date | Jun 28, 2011 |
| Priority date | — |
| Expiry date | May 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.