Transistor and method of manufacturing the same
US7972930B2 · kind B2 · utility
22Cited by
2References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 28, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Nov 16, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer surrounding the channel layer between the source electrode and the drain electrode, and a gate electrode surrounding the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.