Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region
US7973371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of a second conductivity type, which is located between the first well region and the second well region. The memory cell further includes a first tap diffused layer of the first conductivity type for supplying a potential to the first well region, a second tap diffused layer of the first conductivity type for supplying the potential to the second well region, the first and second tap diffused layers being arranged substantially on a diagonal line in the layout of the SRAM cell, and a metal interconnection connected to the first and second tap diffused layers, the metal interconnection passing on the third well region in the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.