Embedded chip package
US7973399B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Aug 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and has a plurality of electrical bonding pads, and the electrical bonding pads contact the dielectric layer. The encapsulating material layer is disposed on the substrate and around the semiconductor structure. In addition, a plurality of conductive vias is disposed in the substrate to electrically connect the patterned circuit layer to the electrical bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.