Manufacturing process and structure of through silicon via
US7973415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2008 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | May 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.