Semiconductor memory device and method for erasing the same
US7974130B2 · kind B2 · utility
13Cited by
6References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Nov 8, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a memory cell array with NAND cell units arranged therein, the NAND cell unit having a plurality of electrically rewritable and non-volatile memory cells connected in series, first and second select gate transistors disposed for coupling the both ends of the NAND cell unit to a bit line and a source line, respectively, and a dummy cell disposed adjacent to at least one of the first and second select gate transistors, wherein after erasing the memory cells in an erase unit, the memory cells excepting the dummy cell are subject to soft-program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.