Non-volatile semiconductor memory device and erasing method thereof
US7974135B2 · kind B2 · utility
1Cited by
7References
11Claims
0Family size
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Key dates
| Filing date | Mar 24, 2009 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Sep 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.