High speed receive equalizer architecture
US7974337B2 · kind B2 · utility
12Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2009 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Oct 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.