Scrambling of a calculation performed according to an RSA-CRT algorithm
US7974408B2 · kind B2 · utility
2Cited by
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5Claims
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Key dates
| Filing date | Aug 29, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Mar 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/7238
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a circuit for scrambling an RSA-CRT algorithm calculation by an electronic circuit, in which a result is obtained from two modular exponentiation calculations, each providing a partial result, and from a recombination step, and in which a first step adds a digital quantity to at least one first partial result before said recombination step; and a second step cancels the effects of this quantity after the recombination step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.