Hardware matrix computation for wireless receivers
US7974997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | May 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/709727
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.