Reducing CPU and bus power when running in power-save modes
US7975161B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2007 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Sep 4, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more bus clock signal frequencies. In a power-save mode, the processor is able to generate one or more core clock signals at frequencies such that the lowest core clock signal frequency is lower than the predetermined multiple of the lowest of the one or more bus clock signal frequencies in performance mode. The processor is able to achieve this by generating the one or more bus clock signals so that the lowest of the bus clock signal frequencies in power-save mode is lower than the lowest of the bus clock signal frequencies in performance mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.