Scan architecture for full custom blocks with improved scan latch
US7975195B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2009 |
| Grant date | Jul 5, 2011 |
| Priority date | — |
| Expiry date | Aug 26, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.