Method using multiple layer annealing cap for fabricating group III-nitride semiconductor device structures and devices formed thereby
US7977224B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Sep 30, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/902
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.