Phase-changeable memory devices having reduced susceptibility to thermal interference
US7977662B2 · kind B2 · utility
9Cited by
2References
7Claims
0Family size
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Key dates
| Filing date | Nov 5, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Jul 2, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.