Semiconductor device
US7977781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2010 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Oct 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction. Communication between the processor LSI 100 and the memory LSI 200 in the same combination is performed by a dedicated electrode provided therebetween, and communication between processor LSIs 100 and communication from the processor LSI 100 to the outside are performed by a through silicon via for signal 11 which passes through all the LSIs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.