Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same
US7978117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.