Setting memory device termination in a memory device and memory controller interface in a communication bus
US7978538B2 · kind B2 · utility
3Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Jan 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and memory controller are coupled during driver training to reduce mismatches. The impedances of the system are controlled through a termination at the memory device to yield improvements in timing margins. The coupling of the components on a shared electrical bus through adjustment of the termination values during training removes known offset issues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.