Memory controller, PCB, computer system and memory adjusting method adjusting a memory output signal characteristic
US7978546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2009 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Aug 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.