Method for verifying connectivity of electrical circuit components
US7979262B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Jul 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets. Verifications can be performed for both digital and mixed signal digital/analog designs without running simulations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.