Quad aware locking primitive
US7979617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2008 |
| Grant date | Jul 12, 2011 |
| Priority date | — |
| Expiry date | Jul 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.